Dual J-K Negative Edge Triggered Flip/Flop
74LS112
$1.32
| QTY | Price |
|---|---|
| 1 | $1.32 |
| 10 | $1.19 |
| 25 | $1.07 |
Description
The 74LS112 dual J-K flip-flop has individual J, K, clock, and asynchronous sets and clear inputs for each flip-flop. When the clock goes HIGH, the inputs are enabled and data is accepted. When the clock pulse is HIGH, the logic level of the J and K inputs can be allowed to change, and the bi-stable will perform according to the truth table as long as the minimum set-up and hold time are observed. On the clock pulse's negative edge, input data is transferred to the outputs.
Specifications
Pins
16
Operating Temperature
0 - 70°C
Supply Voltage
5 V
Terminal Finish
Tin/Lead (Sn/Pb)
Dimensions
Terminal Pitch
2.54 mm
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